A fundamental element of design in digital computers is the use of bi-directional data buses. This system discloses a design to provide reliable data transfer on high-speed digital computer bi-directional buses.
FIG. 3 shows a schematic drawing of a typical digital system bus 60. Modern digital computer systems require wide, high-speed, bi-directional data buses such that the bus 60 of FIG. 3 may, for example, be composed of eight bit lines which would make it a bus of eight bits wide. Likewise, other systems use 16-bit wide buses, and other systems may use 32, 48 and even 64-bit wide buses.
These buses, such as 60, will generally have several data sources and several data receivers on them. Each data source on the bus 60 will use "driver" circuit chips attached to the bus. These are shown schematically as drivers 10.sub.d, 20.sub.d, 30.sub.d, and 40.sub.d in FIG. 3.
These drivers, when not attempting to be a transmitting-source of data on the bus, will-normally be "tri-stated". The tri-state condition of a driver means that it presents a very high impedance to the bus and electrically appears almost as though it were not present.
When a driver is "enabled" in order to present data onto the data bus 60, it is in its "active" state. In the active state it can "source" or "sink" a large quantity of electrical current. Further, with the present state of the art, the modern bus driver chips such as 10.sub.d, . . . 40.sub.d can switch on and off very rapidly,--for example, within a few nanoseconds.
In FIG. 3, each of the computer resources which use the bus will have its driver enabled, such as 10.sub.d, 20.sub.d, 30.sub.d, and 40.sub.d respectively, in order to access the bus 60 and to drive data onto it. This is done via the connecting buses, 12, 22, 32, and 42 respectively.
Likewise, in FIG. 3, when a computer resource is enabled to "receive data" from the bus 60, it is done by means of the receivers such as 10.sub.r, 20.sub.r, 30.sub.r, and 40.sub.r, also through the respective bus connections 12, 22, 32, and 42 which connect to the shared bus 60.
If the situation should arise where more than one driver circuit on the data bus 60 is enabled to drive or dump data onto the bus at the same time, this is called "double drive".
Double drive presents a problem even for extremely small periods of times, even as small as a few nanoseconds, since this can present disturbances to the clean, clear flow of data on the data bus.
As the speed (clock rates) of digital systems increase, the effects of "double drive" become more dangerous to the integrity of data transfer operations. Thus it can be seen that the condition of double drive is a serious problem and requires solutions to enable data transfer with system integrity. The presently described system acts to provide a simple clean-cut and efficiently inexpensive solution to this problem.
The problem can be presented by means of the simplified circuit diagram of FIG. 4 which shows two driver circuits 10.sub.d and 20.sub.d connected to a common or shared bus 60. A data bus may be many bits wide. For example, it is not uncommon to have a 64-bit wide bus for data words.
For example since the entire width of a 56-bit bus (that is to say, each of the 56 lines) is normally switched together at the same time, it may be seen that not one, but many drivers are acting simultaneously in concert, and this provides another conditional situation which amplifies the problem of double drive.
With proper design standards, there is only one driver (that is, one set of source drivers of a bus width) which is allowed to be active on the bus at a given time. As seen in FIG. 4, if a driver is "on", then one of the two transistors (TU or TL) is "on". If TU is on, the driver is putting out a logical "one" (high voltage) onto the bus 60. If TL is on, the driver is putting out a logical "zero" (low voltage-ground) onto the bus.
It will, of course, be observed that if both of the drivers 10.sub.d and 20.sub.d are "on" simultaneously, and if one driver is putting out a logic "one" and the other driver is putting out a logic "zero", then the TU of the one driver is connected to the TL of the other driver. Thus this situation presents practically a dead short between the voltage source and ground. This will cause a very large electrical current to flow and cause a large current spike, which is the cause of many of the system problems associated with double drive and data corruption on the bus.
It should be indicated that FIG. 4 is merely representative in that there is a separate driver, 10.sub.d, for each bit-line of bus 12 so that actually 10.sub.d represents an "associated set" of drivers for the various bit-lines constituting bus 12.
Similarly the second driver 20.sub.d of FIG. 4 represents an "associated set" of drivers for the bit lines of bus 22 which conveys data to the shared system bus 60.
In FIG. 4, it may be noted that each transistor TU and TL operates like an on/off switch. When the transistor TU is "on", then the driver unit, 10.sub.d and/or 20.sub.d, will output a logical "one".
When the transistor TL is "on", then any one of the drivers, 10.sub.d and/or 20.sub.d will output a logical "zero".
"Double-drive" occurs when the transistor TU of one driver is "on" at the same time that the transistor TL of another driver is also "on". Thus there is a time overlap of the "on-ness" of one driver such as 10.sub.d with another driver such as 20.sub.d. This overlapping time period is destructive of the data on the bus 60.
When neither transistor TU or TL is "on", then the driver is put in a condition called "tri-state" which effectively isolates it from connection with the bus 60.
With reference to FIG. 5, there is seen a graph illustrating the "on" time of the first driver 10.sub.d and the second driver 20.sub.d. Since there is an overlap in the "on" times of each of these drivers, it is seen that a spike occurs in the voltage plane and in the ground plane during the overlap period where the "double-drive" time occurs.
The overlap of the two drivers, being enabled simultaneously, can be of very short duration and yet still induce significant system problems on the data bus 60. FIG. 5 indicates the first of several problems which are caused by double-drive on a system bus.
This first problem can be seen as a significant "glitch" on the system supply voltage (voltage plane) and a corresponding voltage spike on the system ground plane. These glitches are undesirable since they may induce noise into other signals and circuits as they propagate throughout the system, with the net result being a potentially unstable system. Failures caused by these type problems are intermittent and difficult to isolate and fix. Additionally, these type of problems can cause data corruption in a computer system which makes the system totally unacceptable.
A second significant problem which may be introduced by the "double-drive" condition is the effect of "slowing down" of the system bus operation. During the time portion of the double-drive, data on the system bus is not stable or even valid for a receiving element to read. Thus, FIG. 6 indicates a "delay effect" caused by the double-drive condition. Line 1 of FIG. 6 shows the system clock periods of operation. Line 2 of FIG. 6 shows the period of time that source data from a transmittal point or transmittal source is available. Line 3 shows the time period during which data is normally received by a receiving unit. Line 4 indicates the delay of received data due to the double-drive condition.
In FIG. 6 it is assumed that data is received on the active (rising) edge of the clock, at time point "d".
The time period (a-b) is the normal propagation delay of the bus signals over the system bus.
The time period (b-d) is the time between the receipt of the data at the receiver and the next rising clock edge. This time is the safety margin for the received data. The receiving device will have a "set-up" time. (For some devices, one example being certain CMOS chips, the set-up time on signals is as great as 45 ns.) However, the safety margin must exceed the receiver's set-up time. For proper system design, the worst case signals and devices must be the design criteria.
In FIG. 6, the time period (b-c) is the additional delay on the received signal caused by the double drive. Compared to FIG. 5, this time period is the time of the glitch and its settling down time. The double drive has caused the bus data to effectively arrive (in a stable condition to be read) at time (c) instead of time (b). It can be seen, therefore, that the "safety margin" time for the receiver has been reduced from (b-d) to (c-d). If (c-d) is now less than the required set-up time of the receiving device, reliable data will not be received.
In modern high-speed computer systems, higher performance is achieved in part by making the clock speeds higher. This causes the clock period to be shorter, thus allowing less time for signal information and bus information to be propagated between logical sections of the system. And strictly by the nature of high-speed transmission lines, data buses require time in order to transmit a stable signal. Double-drive conditions increase the bus transmission time by at least a duration of the "drive overlap" between any two of the resource units connected to the bus. For efficiency purposes, this double-drive delay may put the bus delay over the limit and thus cause "bad" or corrupted data to be read by a receiving resource unit.
A third problem which may be introduced by the double-drive condition is the long term reliability of the bus drivers, such as 10.sub.d, 20.sub.d, . . . 40.sub.d, etc. If the time period of the double-drive is too long, the drivers may actually be destroyed by the very high current coursing through them. But even short of this extreme situation, the more likely problem is that the short, very high current spikes will shorten the life of the driver chips. And this, of course, lowers the long term stability and reliability of the system.
Thus it can be seen that certain serious and undesirable results can be induced because of the double-drive condition. In some past system designs, the double-drive condition could often be easily ignored because (1) the clock rates were slower and thus allowed longer propagation and settling times; (2) the driver circuits were switched more slowly and thus sloppy logic design was masked by slow switching devices; and (3) very expensive voltage distribution schemes with very heavy copper voltage planes and extensive decoupling circuits were used in these older systems.
These mitigating influences are no longer available and valid for systems. The present day logic designer must prevent double-drive, in today's systems, through careful design techniques. Thus the present-system provides a solution which prevents the various intermittent data problems which used to be simply ignored or solved by very expensive voltage/ground plane support systems.
Another situation that occurs is that of the usage of a variety of different types of drivers which have different switching times. FIG. 7 shows a system bus 60 with three different types of driver circuits. Each of the driver circuit units 10.sub.d 20.sub.d. and 30.sub.d are of a different circuit type. This variety becomes very typical as each type meets a different need.
The first driver 10.sub.d (74FCT245 such as designated by Fairchild Semiconductor Company of 333 Western Ave., So. Portland, Me. 04106) is a bi-directional transceiver which allows data transfers in and out using a single chip type. The second driver 20.sub.d (CMOS VLSI device) is a CMOS VLSI chip type. These are custom chips unique to certain specific designs. The third driver, 30.sub.d (74ACT373) is a latch driver which holds data which is to be driven onto the bus 60. There are other possible driver types that also could be used but these are illustrative. It is worthy of notice to see that this variety of types of driver devices can increase the problem of double-drive conditions.
As seen in FIG. 7, the first driver 10.sub.d has a minimum switching time range of 1.5 nanosecond and a maximum switching time range of 9.5 nanoseconds. The second driver 20.sub.d has a minimum switching time range of 4 nanoseconds and a maximum switching time range of 40 nanoseconds, while the third driver 30.sub.d has a minimum time switching range of 1.0 nanoseconds and a maximum time switching range up to 11 nanoseconds. Thus each driver circuit type has a different switching time characteristic. For some chip technologies, the range of the switching times is very broad. This makes "predicting" the time a driver will go "on" or go "off" of the bus 60, to be an inexact situation.
FIG. 8 shows an example of two drivers which are enabled/disabled at the exact same instant of time and yet may still cause a considerable spike of double-drive condition due to the switching time differences. As seen in FIG. 8, the first or top line shows the first driver switching from "off" to "on" to turn onto connection with the bus 60. Likewise, the second driver (shown on line 3) is transitioning from "on" to "off" in order to disconnect from connection with the bus 60. It is seen that the time period (a-b) is the switching time for the first driver to position from its "off" position to its "on" position in order to connect to the bus. The actual switching may occur anywhere within the time period between a and b.
Likewise, (on the fourth line) it is seen that the second driver, which is switching from "on" the bus to "off" the bus, has a time period (a-c) which presents a time lag where it is unknown at what actual instant the disconnection will occur. Thus it is seen that the time period (a-b) is a period of uncertainty in which two of the drivers are in the process of transitioning and double drive problems can occur since both drivers may still be connected to the bus 60.
In addition to the variety of different driver circuit types, there occur the differences in the generation of the various "driver enable" signals which control the driver circuit units. Each driver signal has a unique group of logic functions within it. It also must propagate over its own unique logic path. Thus each driver is implemented in its own unique group of logic devices. These provide factors which combine to make exact control of the driver chips somewhat difficult to predict.
FIG. 9 shows an example where the switching times of two drivers are assumed to be "instantaneous". But since the "enable" signals are actually different in time-occurrence, this also introduces the possibility of a double-drive condition.
For example, in FIG. 9, when the first driver is transitioning from "off" to "on", it must be initiated by the enable 1 signal shown in the top line of FIG. 9. Thus, at time (a) the first driver turns "on". Now when it is desired for the second driver to transition from the "on" to the "off" condition, it is seen that the enable 2 signal has a longer operation time (line 3) and does not operate until the time point b in order to turn off the second driver. Thus the time period (a-b) is the delay time of the enable 2 signal. Thus a condition is provided during the time period (a-b) where there is a possible double-drive condition.
By observation of FIG. 9, it can be deduced that one part of the solution to the double-drive problem is to always have a situation where the driver which is turning "off" precedes the driver which is turning."on". That is to say, the disconnection of a driver from the bus 60 should occur "before" the actual connection of the other driver onto the bus 60.